Power Forward Initiative Low-Power Design Summit

Thank you for supporting the 2008 Power Forward Low-Power Design Summit. An overwhelming number of you responded and attended this event. You can now download a copy of the proceedings. If you have further questions or would like to talk to the Power Forward members send an email to powerforward@cadence.com.

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October 1, 2008 proceedings

Introduction - Pankaj Mayor, Cadence

Keynote: nPowering Change - Chris Malachowsky, NVIDIA

Track 1 - Low-Power Design in Action

Power-Gating on a High Performance GPU - Jeffrey Yang, AMD

Low-Power Design Considerations - David Lan, TSMC

ARM1176-JZFS CPU Based Low-Power Subsystem; Methodology to Reduce Electrical and Functional Failure - Sachin Idgunji, ARM Inc., Helder Mak, Cadence, David Flynn, ARM Inc., Peter CP Sun, UMC, Felix Jen, UMC.

Advanced Low-Power Design - Tobing Soebroto, Cadence

Track 2 - Power Optimized IP

Power-efficient Sound Solutions from ARC - Akash Despande, ARC International

ARM Power Management Kit and iRM - Wolfgang Helfricht, ARM Inc.

CPF Flow for Highly-configurable Interconnect IP - Scott Evans, Sonics, Inc.

Minimizing Design Complexity with Power Optimized Physical IP - Ken Brock, Virage Logic

Panel: Deploying Low Power - What are the Challenges?

Moderator: Susan Runowicz-Smith, Cadence

Panelists: Ameesh Desai, LSI; Anis Jarrar, Freescale Semiconductor;

Herve Menager, NXP; Brani Buric, Virage Logic

Track 3 - Low-Power Design Applications

Ultra Low-Power Implementation using CPF - Anis Jarrar, Freescale Semiconductor

Faraday: A Low-Power Platform-based SoC - Albert Chen, Faraday Technology Corporation

Cadence 45nm Common Platform Reference Flow - Gary Cheung, Chartered Semiconductor

Pre-Design ASIC Power Estimates - Bob Eisenstadt, Alchip Technologies

Track 4 - Architectural Low-Power Trade-off Techniques

Architectural Trade-off Analysis - Thad McCracken, Chip Planning Solutions

Sequential Optimizations for Low Power - Anmol Mathur, Calypto

Early Power Analysis with CPF - Will Ruby, Sequence Design

Micro-Architecture Power Tradeoffs at the Electronic System Level - Michael McNamara, Cadence

Keynote: Clean and Green - Carl Guardino, Silicon Valley Leadership Group

Panel: Enabling Power-Efficient Design - How Important is it to be Green?

Moderator: Ron Wilson, EDN Executive Editor

Panelists: John Goodenough, ARM; Walter Ng, Chartered Semiconductor; Steve Carlson, Cadence; Carl Guardino, Silicon Valley Leadership Group, Ron Burns, Wipro

		Power-Gating on a High Performance GPU - Jeffrey Yang, AMD
		Low-Power Design Considerations - David Lan, TSMC
		ARM1176-JZFS CPU Based Low-Power Subsystem; Methodology to Reduce Electrical and Functional Failure - Sachin Idgunji, ARM Inc., Helder Mak, Cadence, David Flynn, ARM Inc., Peter CP Sun, UMC, Felix Jen, UMC.
		Advanced Low-Power Design - Tobing Soebroto, Cadence

		Power-efficient Sound Solutions from ARC - Akash Despande, ARC International
		ARM Power Management Kit and iRM - Wolfgang Helfricht, ARM Inc.
		CPF Flow for Highly-configurable Interconnect IP - Scott Evans, Sonics, Inc.
		Minimizing Design Complexity with Power Optimized Physical IP - Ken Brock, Virage Logic

	Moderator: Susan Runowicz-Smith, Cadence
	Panelists: Ameesh Desai, LSI; Anis Jarrar, Freescale Semiconductor;
	Herve Menager, NXP; Brani Buric, Virage Logic

		Ultra Low-Power Implementation using CPF - Anis Jarrar, Freescale Semiconductor
		Faraday: A Low-Power Platform-based SoC - Albert Chen, Faraday Technology Corporation
		Cadence 45nm Common Platform Reference Flow - Gary Cheung, Chartered Semiconductor
		Pre-Design ASIC Power Estimates - Bob Eisenstadt, Alchip Technologies

		Architectural Trade-off Analysis - Thad McCracken, Chip Planning Solutions
		Sequential Optimizations for Low Power - Anmol Mathur, Calypto
		Early Power Analysis with CPF - Will Ruby, Sequence Design
		Micro-Architecture Power Tradeoffs at the Electronic System Level - Michael McNamara, Cadence

	Moderator: Ron Wilson, EDN Executive Editor
	Panelists: John Goodenough, ARM; Walter Ng, Chartered Semiconductor; Steve Carlson, Cadence; Carl Guardino, Silicon Valley Leadership Group, Ron Burns, Wipro

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Power Forward Initiative Low-Power Design Summit